1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor memory device including a repair fuse circuit.
2.Description of the Related Art
Generally, a semiconductor memory device including a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) includes a large number of memory cells. As the integration degree of the semiconductor memory device increases by the advancement of fixing technology, it has greater number of memory cells. If there is even one defective memory cell among the numerous number of memory cells mounted on a semiconductor memory device, the semiconductor memory device may not perform an intended operation and may be abandoned. As semiconductor memory device fabrication technology develops, few number of memory cells may be defective. Nevertheless, abandoning the whole semiconductor memory device due to such memory cells may decrease production yield. Therefore, a semiconductor memory device is typically provided with a redundancy memory cell along with normal memory cells.
A redundancy memory cell may be a memory cell provided for the purpose of replacing a defective memory cell of normal memory cells. Specifically, when a defective memory cell occurs among the normal memory cells and it is accessed, the redundancy memory cell which operates as a normal memory cell is accessed instead of the defective memory cell. Although an address corresponding to a defective memory cell is inputted in a semiconductor memory device, the semiconductor memory device may secure a desired operation by using the redundancy memory cell and making the redundancy memory cell accessed. Hereinafter, the defective memory cell, which is a memory cell with a defect, is referred to as a ‘repair target memory cell.’
Meanwhile, the semiconductor memory device includes other circuits, such as a repair fuse circuit, together with the redundancy memory cell to perform a repair operation. The repair fuse circuit stores an address corresponding to a repair target memory cell, which is, hereinafter, referred to as a ‘repair target address.’ Each of the fuses in the repair fuse circuit is programmed with the repair target address. The semiconductor memory device performs a repair operation based on the programmed repair target address.
For example, programming a fuse means a series of operations for storing an address data in a fuse. Generally, a method for programming includes a laser cutting method and an electrical cutting method. The laser cutting method is a method of cutting a line with a laser beam by blowing a fuse based on an address data, and the electrical cutting method is a method of cutting a line by applying an overcurrent to a fuse and melting the fuse based on an address data. The laser cutting method is relatively simple, compared with an electrical cutting method. However, the laser cutting method may be typically performed in the stage of wafer, which is a stage before the semiconductor memory device is fabricated as a package.
FIG. 1 is a block diagram illustrating a redundancy circuit of a conventional semiconductor memory device.
Referring to FIG. 1, the redundancy circuit includes a plurality of repair fuse units 110, a plurality of address comparison units 120, and an enable fuse unit 130.
Each of the repair fuse units 110 is programmed with a repair target address corresponding to a repair target memory cell. Each of the address comparison units 120 compares an address ADD<0:N>, where N is a natural number, with a corresponding fuse address FU_ADD<0:N>, among a plurality of fuse addresses that are respectively outputted from the repair fuse units 110, and generates a repair decision signal HIT_SUM<0:M>. The fuse addresses FU_ADD<0:N>are respectively programmed in the repair fuse units 110, and the fuse addresses FU_ADD<0:N> correspond to repair target addresses, respectively. Subsequently, the enable fuse unit 130 generates an enable signal FU_EN<0:M>, where M is a natural number, depending on whether the repair fuse units 110 are programmed or not. Whether to enable the enable signal FU_EN<0:M> is decided depending on whether the repair fuse units 110 are programmed or not.
Each of the repair fuse units 110 includes a plurality of fuse circuits. FIG. 1 shows a semiconductor memory device where an address is formed of N+1 bits and M+1 addresses are programmed. In short, the repair fuse units 110 include (N+1)×(M+1) fuse circuits.
Meanwhile, the semiconductor memory device includes fuse circuits for diverse purposes other than such repair fuse circuits. The fuse circuits for diverse purposes include a tuning fuse circuit which is used for tuning a voltage in a static voltage generation circuit that operates sensitively responding to an environment, a test fuse circuit that is used for testing, and a control fuse circuit for controlling diverse mode selections. The fuse circuits may be designed in the semiconductor memory device separately from the repair fuse circuit.
The number of memory cells mounted on a semiconductor memory device is increasing so that the number of repair fuse circuits and the number of fuse circuits for storing data may be increased. In the trend that the size of semiconductor memory devices becomes small, such an increase in the number of repair fuse circuit and in the number of other fuse circuits may be obstacle to prevent the size of the semiconductor memory devices from being reduced.